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19-3200; Rev 2; 10/08
KIT ATION EVALU ILABLE AVA
Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
General Description Features
o Dual Quick-PWM with Fast Transient Response o Automatic Dynamic REFIN1 Detection and PGOOD1/Fault Blanking o Fixed and Adjustable Output Voltages 0.7% Output Accuracy Over Line and Load OUT1: 0 to 2V Dynamic Output or Preset 1.05V OUT2: 0.7V to 2V Range or Preset 1.5V o Resistor-Programmable Switching Frequency o Integrated BST Switches o Differential Current-Sense Inputs Low-Cost DCR Sensing or Accurate CurrentSense Resistors Internally Coupled Current-Sense Compensation o Combinable Mode Supports High-Current Dynamic Output Voltages o Selectable Forced-PWM, Pulse Skip, or Ultrasonic Mode Operation o 26V Maximum Input Voltage Rating o Independent Enable Inputs o Independent Power-Good Outputs o Overvoltage Protection (MAX17007A Only) o Undervoltage/Thermal Protection o Voltage Soft-Start and Soft-Shutdown
The MAX17007A/MAX17008 are dual Quick-PWMTM step-down controllers intended for general power generation in battery-powered systems. The two switchedmode power supplies (SMPSs) can also be combined to operate in a two-phase single-output mode. Constant on-time Quick-PWM operation provides fast response to load transients and handles wide input/output (I/O) voltage ratios with ease, while maintaining a relatively constant switching frequency. The switching frequency can be individually adjusted between 200kHz and 600kHz with external resistors. Differential output current sensing allows output sense-resistor sensing for an accurate current limit, or lossless inductor direct-current resistance (DCR) current sensing for lower power dissipation while maintaining 0.7% output accuracy. Overvoltage (MAX17007A only), undervoltage protection, and accurate user-selectable current limits (15mV, 30mV, 45mV, and 60mV) ensure robust operations. The SMPS outputs can operate in skip mode or in ultrasonic mode for improved light-load efficiency. The ultrasonic mode eliminates audible noises by maintaining a minimum switching frequency of 25kHz in pulseskipping mode. The output voltage of SMPS1 can be dynamically adjusted by changing the voltage at the REFIN1 pin. The device includes a 0.5% accurate reference output that can be used to set the REFIN1 voltage. An external 5V bias supply is required to power the internal circuitry and its gate drivers. Independent on/off controls with well-defined logic thresholds and independent open-drain power-good outputs provide flexible system configurations. To prevent current surges at startup, the internal voltage target is slowly ramped up from zero to the final target with a slew rate of 1.3mV/s for SMPS1 at CSL1 and 0.65mV/s for SMPS2 at FB2. To prevent the output from ringing off below ground in shutdown, the internal voltage target is ramped down from its previous value to zero with the same respective slew rates. Integrated bootstrap switches eliminate the need for external bootstrap diodes. The MAX17007A/MAX17008 are available in a spacesaving, 28-pin, 4mm x 4mm, thin QFN package with an exposed backside pad.
Ordering Information
PART MAX17007AGTI+ TEMP RANGE -40C to +105C PIN-PACKAGE 28 Thin QFN-EP*
MAX17008GTI+ -40C to +105C 28 Thin QFN-EP* +Denotes a lead-free/RoHS-compliant package. *EP = Exposed pad.
Pin Configuration
PGND BST2 TOP VIEW 21 LX2 22 DH2 23 PGOOD2 24 EN2 25 CSH2 26 CSL2 27 *EP FB2 28 + 1 REF 2 ILIM1 3 (CCI) ILIM2 4 VCC 5 SKIP 6 TON1 7 TON2 8 REFIN1 20 19 18 17 16 15 14 LX1 13 DH1 12 PGOOD1 BST1 11 EN1 10 CSH1 9 CSL1 GND DL2 DL1 VDD
MAX17007A MAX17008
Applications
Notebook Computers Low-Power I/O Supplies GPU Core Supplies
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
2 to 4 Li+ Cells BatteryPowered Devices
THIN QFN (4mm x 4mm) *EP = EXPOSED PAD.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
ABSOLUTE MAXIMUM RATINGS
BST1, BST2 to GND ...............................................-0.3V to +34V BST1, BST2 to VDD .................................................-0.3V to +28V TON1, TON2 to GND..............................................-0.3V to +28V VDD to GND ..............................................................-0.3V to +6V VDD to VCC ............................................................-0.3V to +0.3V LX1 to BST1..............................................................-6V to +0.3V LX2 to BST2..............................................................-6V to +0.3V DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V) DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V) ILIM1, ILIM2, REF to GND ..........................-0.3V to (VCC + 0.3V) CSH1, CSH2, CSL1, CSL2, FB2, REFIN1 to GND....-0.3V to +6V EN1, EN2, SKIP, PGOOD1, PGOOD2 to GND.........-0.3V to +6V DL1 to GND ................................................-0.3V to (VDD + 0.3V) DL2 to PGND..............................................-0.3V to (VDD + 0.3V) PGND to GND ......................................................-0.3V to + 0.3V REF Short Circuit to GND ...........................................Continuous Continuous Power Dissipation (TA = +70C) 28-Pin TQFN T2844-1 (derate 20.8mW/C above +70C) ............................1667mW Extended Operating Temperature Range .........-40C to +105C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 12V, VDD = VCC = VEN1 = VEN2 = 5V, VREFIN1 = 2V, SKIP = GND, TA = 0 to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER PWM CONTROLLER Input Voltage Range Quiescent Supply Current (VDD, VCC) Shutdown Supply Current (VDD, VCC) VIN IDD + ICC I SHDN Output forced above regulation voltage, VEN1 = VEN2 = 5V EN1 = EN2 = GND, TA = +25C VIN = 12V, VCSL1 = VCSL2 = VCCI = 1.2V, separate or combined mode (Note 1) EN1 = EN2 = GND, VTON1 = VTON2 = 26V, VDD = 0 or 5V, TA = +25C (Note 2) Adjustable mode Preset mode Combined mode 1.7 3.8 3.8 IREFIN1, IFB2 VCSL1 SMPS1 Voltage Accuracy VCSL1 VREFIN1 REFIN1 = 0.5V to 2V; VFB2 = 0.7V, TA = +25C Measured at CSL1, REFIN1 = VCC, VIN = 2V to 26V, SKIP = VCC (Note 2) REFIN1 = 500mV, SKIP = VCC TA = +25C TA = 0C to +85C -0.1 1.043 -12 -20 -20 1.05 VCC 1V VCC 1V 0 0.7 2.3 VCC 0.4 VCC 0.4 +0.1 1.057 +12 +20 +20 mV RTON1 = RTON2 = 97.5k (600kHz) RTON1 = RTON2 = 200k (300kHz) RTON1 = RTON2 = 302.5k (200kHz) 142 (-15%) 305 (-10%) 425 (-15%) 4.5 1.7 0.1 174 336 500 250 0.01 26 2.5 5 194 (+15%) 368 (+10%) 575 (+15%) 400 1 VREF ns A V V V V V A V ns V mA A SYMBOL CONDITIONS MIN TYP MAX UNITS
On-Time (Note 1)
t ON1, t ON2
Minimum Off-Time TON1, TON2, Shutdown Supply Current REFIN1 Voltage Range FB2 Regulation Voltage FB2 Input Voltage Range FB2 Combined-Mode Threshold REFIN1 Dual ModeTM Switchover Threshold REFIN1, FB2 Bias Current
t OFF(MIN) ITON1, ITON2 VREFIN1 VFB2
REFIN1 = 2V, SKIP = VCC
Dual Mode is a trademark of Maxim Integrated Products, Inc.
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, VDD = VCC = VEN1 = VEN2 = 5V, VREFIN1 = 2V, SKIP = GND, TA = 0 to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SMPS2 Voltage Accuracy Load Regulation Error Line Regulation Error CSL1 Soft-Start/-Stop Slew Rate FB2 Soft-Start/-Stop Slew Rate Dynamic REFIN1 Slew Rate INTERNAL REFERENCE Reference Voltage Reference Lockout Voltage Reference Load Regulation FAULT DETECTION SMPS1 Overvoltage Trip Threshold and PGOOD1 Upper Threshold (MAX17007A Only) SMPS2 Adjustable Mode Overvoltage Trip Threshold and PGOOD2 Upper Threshold (MAX17007A Only) Output Overvoltage Fault Propagation Delay (MAX17007A Only) SMPS1 Undervoltage Protection Trip Threshold and Lower PGOOD1 Threshold SMPS2 Undervoltage Protection Trip Threshold and Lower PGOOD2 Threshold Output Undervoltage Fault Propagation Delay PGOOD_ Propagation Delay PGOOD_ Output Low Voltage PGOOD_ Leakage Current Dynamic REFIN1 Transition Fault-Blanking Threshold Thermal-Shutdown Threshold VCC Undervoltage Lockout Threshold T SHDN I PGOOD With respect to the internal target voltage (error comparator threshold); rising edge; hysteresis = 50mV Dynamic transition Minimum OVP threshold VOVP2, VPG2_H With respect to the internal target voltage 0.7V (error comparator threshold); hysteresis = 50mV CSL1/FB2 forced 25mV above trip threshold With respect to the internal target voltage (error comparator threshold); falling edge; hysteresis = 50mV With respect to the internal target voltage 0.7V (error comparator threshold); falling edge; hysteresis = 50mV CSL1/FB2 forced 25mV below trip threshold UVP falling edge, 25mV overdrive t PGOOD OVP rising edge, 25mV overdrive Startup delay from regulation I SINK = 3mA CSL1 = REFIN1, FB2 = 0.7V (PGOOD_ high impedance), PGOOD_ forced to 5V, TA = +25C Fault blanking initiated; REFIN1 deviation from the internal target voltage (error comparator threshold); hysteresis = 10mV Hysteresis = 15C (Note 3) 3.95 50 160 4.20 4.45 90 120 260 300 VREF + 0.30 0.7 150 180 340 mV V V mV VREF VREF(UVLO) VDD = 4.5V to 5.5V Rising edge, hysteresis = 230mV IREF = -10A to +100A 1.980 1.990 2.000 1.8 2.015 2.010 V V mV SRSS1 SRSS2 SRDYN SYMBOL VCSL2 CONDITIONS Measured at CSL2, FB2 = REF, VIN = 2V to 26V, SKIP = VCC ILOAD = 0 to full load, SKIP = VCC (Note 3) VDD = 4.5V to 5.5V, VIN = 4.5V to 26V (Note 3) Rising/falling edge on EN1 Rising/falling edge on EN2 Rising edge on REFIN1 MIN 1.489 TYP 1.5 0.1 0.25 1.25 0.63 11.4 MAX 1.511 UNITS V % % mV/s mV/s mV/s
MAX17007A/MAX17008
VOVP1, VPG1_H
t OVP VUVP1, VPG1_L VUVP2, VPG2_L tUVP
5
s
-240
-200
-160
mV
-130 90
-100 205 5 5 205
-70 360
mV s
s 360 0.4 1 V A
mV C V
Rising edge, PWM disabled below this level, VUVLO(VCC) hysteresis = 100mV
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, VDD = VCC = VEN1 = VEN2 = 5V, VREFIN1 = 2V, SKIP = GND, TA = 0 to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER CURRENT LIMIT Current-Sense Input Range Current-Sense Input (CSH_) Leakage Current Current-Sense Input (CSL_) Leakage Current CSH1, CSH2 CSL1, CSL2 CSH_ = GND or VCC, TA = +25C CSL_= CSL_ = 2V, TA = +25C TA = +25C VCSH_ - VCSL_ ILIM1 = ILIM2 = REF TA = 0C to +85C Current-Limit Threshold (Fixed) VCSLIMIT VCSH_ - VCSL_, ILIM1 = ILIM2 = VCC VCSH_ - VCSL_, ILIM1 = ILIM2 = OPEN VCSH_ - VCSL_, ILIM1 = ILIM2 = GND Current-Limit Threshold (Negative) Current-Limit Threshold (Zero Crossing) Ultrasonic Frequency Ultrasonic Current-Limit Threshold Current-Balance Amplifier (GMI) Offset Current-Balance Amplifier (GMI) Transconductance GATE DRIVERS DH1, DH2 Gate-Driver On-Resistance DL1, DL2 Gate-Driver On-Resistance DH1, DH2 Gate-Driver Source/Sink Current DL1, DL2 Gate-Driver Source Current DL1, DL2 Gate-Driver Sink Current Driver Propagation Delay R ON(DH) R ON(DL) IDH BST_ - LX_ forced to 5V High state (pullup) Low state (pulldown) DH_ forced to 2.5V, BST_ - LX_ forced to 5V Low state (pulldown) High state (pullup) 1.7 1.7 1.3 0.6 1.2 1 2.4 10 15 25 30 40 45 4.0 4.0 3.0 2.5 A A A ns VNEG VZX VCSH_ - VCSL_, SKIP = VCC VCSH_ - VCSL_, SKIP = GND or OPEN; ILIM1 = ILIM2 = REF SKIP = OPEN (3.3V); VCSL1 = VREFIN1 + 50mV; VCSL2 = VFB2 + 50mV SKIP = OPEN (3.3V) VCSL1 = VREF1 + 50mV VCSL2 = VFB2+ 50mV 20 22 18 -3 33 30 46 46 +3 28 27 56 42 13 30 30 60 45 15 -1.2 x VCSLIMIT 1 0 0 -0.2 2.3 2.3 +0.2 1 32 33 64 48 17 mV mV kHz mV mV mV V A A SYMBOL CONDITIONS MIN TYP MAX UNITS
[V(CSH1,CSL1) - V(CSH2,CSL2)] at ICCI = 0 ICCI/ [V(CSH1,CSL1) - V(CSH2,CSL2)]; VCCI = VCSL1 = VCSL2 = 0.5V to 2V, and V(CSH_,CSL_) = -60.0mV to +60.0mV, ILIM1 = GND
180
S
IDL(SOURCE) DL_ forced to 2.5V IDL(SINK) DL_ forced to 2.5V DH_ low to DL high DL_ low to DH high
4
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, VDD = VCC = VEN1 = VEN2 = 5V, VREFIN1 = 2V, SKIP = GND, TA = 0 to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DL_ Transition Time DH_ Transition Time Internal BST_ Switch On-Resistance INPUTS AND OUTPUTS EN1, EN2 Logic-Input Threshold Logic-Input Current EN1, EN2 rising edge, hysteresis = 300mV/600mV (min/max) EN1, EN2, TA = +25C High (5V) Quad-Level Input-Logic Levels SKIP, ILIM1, ILIM2 Open (3.3V) Ref (2.0V) Low (GND) Quad-Level Logic-Input Current SKIP, ILIM1, ILIM2 forced to GND or VCC, TA = +25C -2 1.20 -0.5 VCC 0.3 3.0 1.7 3.6 2.3 0.4 +2 A V 1.70 2.20 +0.5 V A RBST_ SYMBOL CONDITIONS DL_ falling, CDL = 3nF DL_ rising, CDL = 3nF DH_ falling, CDH = 3nF DH_ rising, CDH = 3nF IBST_ = 10mA, VDD = 5V MIN 10 10 10 10 TYP 20 20 20 20 6.5 11.0 MAX UNITS ns ns
MAX17007A/MAX17008
ELECTRICAL CHARACTERISTICS
(VIN = 12V, VDD = VCC = VEN1 = VEN2 = 5V, VREFIN1 = 2V, SKIP = GND, TA = -40C to +105C, unless otherwise noted.) (Note 4)
PARAMETER PWM CONTROLLER Input Voltage Range Quiescent Supply Current (VDD, VCC) VIN IDD + ICC Output forced above regulation voltage, VEN1 = VEN2 = 5V VIN = 12V, VCSL1 = VCSL2 = VCCI = 1.2V, separate or combined mode (Note 1) 0 Preset mode Combined mode IREFIN1, IFB2 1.7 3.75 -0.1 RTON1 = RTON2 = 97.5k (600kHz) RTON1 = RTON2 = 200k (300kHz) RTON1 = RTON2 = 302.5k (200kHz) 142 305 425 4.5 26 2.5 194 368 575 400 VREF 2.3 VCC 0.4 +0.1 ns V V V A ns V mA SYMBOL CONDITIONS MIN MAX UNITS
On-Time (Note 1)
t ON1, t ON2
Minimum Off-Time REFIN1 Voltage Range FB2 Input Voltage Range FB2 Combined-Mode Threshold REFIN1, FB2 Bias Current
t OFF(MIN) VREFIN1
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, VDD = VCC = VEN1 = VEN2 = 5V, VREFIN1 = 2V, SKIP = GND, TA = -40C to +105C, unless otherwise noted.) (Note 4)
PARAMETER REFIN1 Dual-Mode Switchover Threshold SMPS1 Voltage Accuracy SMPS2 Voltage Accuracy INTERNAL REFERENCE Reference Voltage FAULT DETECTION SMPS1 Overvoltage Trip Threshold and PGOOD1 Upper Threshold (MAX17007A Only) SMPS2 Overvoltage Trip Threshold and PGOOD2 Upper Threshold (MAX17007A Only) SMPS1 Undervoltage Protection Trip Threshold and Lower PGOOD1 Threshold SMPS2 Undervoltage Protection Trip Threshold and Lower PGOOD2 Threshold Output Undervoltage Fault Propagation Delay PGOOD_ Propagation Delay PGOOD_ Output Low Voltage VCC Undervoltage Lockout Threshold CURRENT LIMIT Current-Sense Input Range Current-Limit Threshold (Fixed) Ultrasonic Frequency Ultrasonic Current-Limit Threshold Current-Balance Amplifier (GMI) Offset VCSLIMIT CSH1, CSH2 CSL1, CSL2 VCSH_ - VCSL_, ILIM1 = ILIM2 = REF SKIP = OPEN (3.3V); VCSL1 = VREFIN1 + 50mV; VCSL2 = VFB2 + 50mV SKIP = OPEN (3.3V) VCSL1 = VREF1 + 50mV VCSL2 = VFB2 + 50mV 0 0 27 18 22 18 -3 46 46 +3 2.3 2.3 33 V mV kHz VUVLO(VCC) VOVP1, VPG1_H With respect to the internal target voltage (error comparator threshold); rising edge; hysteresis = 50mV With respect to the internal target voltage 0.7V (error comparator threshold); hysteresis = 50mV With respect to the internal target voltage (error comparator threshold) falling edge; hysteresis = 50mV With respect to the internal target voltage 0.7V (error comparator threshold) falling edge; hysteresis = 50mV REFIN1/FB2 forced 25mV below trip threshold Startup delay from regulation I SINK = 3mA Rising edge, PWM disabled below this level; hysteresis = 100mV 3.8 VREF VDD = 4.5V to 5.5V 1.985 2.015 V VCSL1 VCSL2 Measured at CSL1, REFIN1 = VCC; VIN = 2V to 26V, SKIP = VCC (Note 2) Measured at CSL2, FB2 = REF; VIN = 2V to 26V, SKIP = VCC (Note 2) SYMBOL CONDITIONS MIN 3.75 1.039 1.485 MAX VCC 0.4 1.061 1.515 UNITS V V V
260
340
mV
VOVP2, VPG2_H
120
180
mV
VUVP1, VPG1_L VUVP2, VPG2_L tUVP t PGOOD
-240
-160
mV
-130
-70
mV
90 90
360 360 0.4 4.45
s s V V
mV mV
[V(CSH1,CSL1) - V(CSH2,CSL2)] at ICCI = 0
6
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, VDD = VCC = VEN1 = VEN2 = 5V, VREFIN1 = 2V, SKIP = GND, TA = -40C to +105C, unless otherwise noted.) (Note 4)
PARAMETER GATE DRIVERS DH1, DH2 Gate-Driver On-Resistance DL1, DL2 Gate-Driver On-Resistance Driver Propagation Delay Internal BST_ Switch On-Resistance INPUTS AND OUTPUTS EN1, EN2 Logic-Input Threshold EN1, EN2 rising edge; hysteresis = 300mV/600mV (min/max) High (5V) Quad-Level Input Logic Levels SKIP, ILIM1, ILIM2 Open (3.3V) Ref (2.0V) Low (GND) 1.20 VCC 0.3 3.0 1.7 3.6 2.3 0.4 V 2.20 V RBST_ R ON(DH) R ON(DL) BST_ - LX_ forced to 5V High state (pullup) Low state (pulldown) DH_ low to DL high DL_ low to DH high IBST_ = 10mA, VDD = 5V 8 12 Low state (pulldown) High state (pullup) 4.5 4.0 3 2.5 42 48 12 ns SYMBOL CONDITIONS MIN MAX UNITS
MAX17007A/MAX17008
Note 1: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = GND, VBST = 5V, and a 250pF capacitor connected from DH to LX. Actual in-circuit times might differ due to MOSFET switching speeds. Note 2: The 0 to 0.5V range is guaranteed by design, not production tested. Note 3: Not production tested. Note 4: Specifications at TA = -40C to +105C are guaranteed by design, not production tested.
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
Typical Operating Characteristics
(Circuit of Figure 1, VIN = 12V, VDD = 5V, SKIP = GND, TA = +25C, unless otherwise noted.)
SMPS2 1.5V EFFICIENCY vs. LOAD CURRENT
MAX17007A/8 toc01
SMPS2 1.5V EFFICIENCY vs. LOAD CURRENT
90 80 EFFICIENCY (%) 70 60 50 40 PWM MODE 30 ULTRASONIC MODE SKIP MODE
MAX17007A/8 toc02
SMPS2 1.5V OUTPUT VOLTAGE vs. LOAD CURRENT
MAX17007A/8 toc03
100 6V 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0.01 0.1 1 LOAD CURRENT (A) 10 SKIP MODE PWM MODE 12V 20V
100
1.54
ULTRASONIC MODE OUTPUT VOLTAGE (V) 1.52 SKIP MODE 1.50 PWM
20 10 VIN = 12V 0.01 0.1 1 LOAD CURRENT (A) 10 100 1.48 0
VIN = 12V 5 10 15
100
LOAD CURRENT (A)
COMBINED 1.2V EFFICIENCY vs. LOAD CURRENT
MAX17007A/8 toc04
COMBINED 1.2V OUTPUT VOLTAGE vs. LOAD CURRENT
VIN = 12V 1.21 PWM 1.20 SKIP MODE 1.19
MAX17007A/8 toc05
SMPS2 SWITCHING FREQUENCY vs. LOAD CURRENT
MAX17007A/8 toc06
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0.01 0.1 1 LOAD CURRENT (A) 10 SKIP MODE PWM MODE 12V 20V 6V
1.22
350 300 250 200 150 100 50 ULTRASONIC MODE SKIP MODE 0.01 0.1 1 LOAD CURRENT (A) 10 VIN = 12V PWM MODE
SWITCHING FREQUENCY (kHz)
OUTPUT VOLTAGE (V)
1.18 100 0 4 8 12 16 20 24 28 LOAD CURRENT (A)
0
100
SMPS2 SWITCHING FREQUENCY vs. INPUT VOLTAGE
MAX17007A/8 toc07
SMPS2 SWITCHING FREQUENCY vs. TEMPERATURE
MAX17007A/8 toc08
SMPS2 MAXIMUM OUTPUT CURRENT vs. INPUT VOLTAGE
MAX17007A/8 toc09
350
330
14 MAXIMUM OUTPUT CURRENT (A)
SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
300
IOUT2 = 5A
310
IOUT2 = 5A
13
IOUT2 = 0A 250
290
12
270 VIN = 12V SKIP = 5V -40 -20 0 20
IOUT2 = 0A
11
200 0
VIN = 12V SKIP = 5V 4 8 12 16 20 24 28
250 INPUT VOLTAGE (V)
10 40 60 80 100 120 0 4 8 12 16 20 24 28 TEMPERATURE (C) INPUT VOLTAGE (V)
8
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VDD = 5V, SKIP = GND, TA = +25C, unless otherwise noted.)
SMPS2 MAXIMUM OUTPUT CURRENT vs. TEMPERATURE
MAX17007A/8 toc10
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
MAX17007A/8 toc11
NO-LOAD INPUT CURRENT vs. INPUT VOLTAGE
EN1 = HIGH EN2 = LOW
MAX17007A/8 toc12 MAX17007A/8 toc15
14 MAXIMUM OUTPUT CURRENT (A)
16 14 SUPPLY CURRERT (IBIAS) (mA) PWM MODE 12 10 8 6 4 2 ULTRASONIC MODE SKIP MODE EN1 = HIGH EN2 = LOW
100 PWM MODE INPUT CURRENT (mA) 10 ULTRASONIC MODE 1
13
12
11
0.1
SKIP MODE
10 -40 -20 0 20 40 60 80 TEMPERATURE (C)
VIN = 12V 100 120
0 4 8 12 16 20 24 INPUT VOLTAGE (V)
0.01 4 6 8 10 12 14 16 18 20 22 24 INPUT VOLTAGE (V)
REFERENCE VOLTAGE vs. REFERENCE LOAD CURRENT
MAX17007A/8 toc13
REFIN1 TO CSL1 OFFSET VOLTAGE DISTRIBUTION
MAX17007A/8 toc14
SMPS1 PRESET 1.05V VOLTAGE DISTRIBUTION
90 80 SAMPLE PERCENTAGE (%) 70 60 50 40 30 20 10 TA = +85C TA = +25C SAMPLE SIZE = 100
2.05
90 80 SAMPLE PERCENTAGE (%) 70 60 50 40 30 20 10 TA = +85C TA = +25C SAMPLE SIZE = 100
REFERENCE VOLTAGE (V)
2.03
2.01
1.99
1.97
1.95 -20 0 20 40 60 80 100 REFERENCE LOAD CURRENT (A)
0 -5.0 -3.0 -1.0 1.0 3.0 5.0 OFFSET VOLTAGE (mV)
0 1.045
1.047
1.049
1.051
1.053
1.055
SMPS1 VOLTAGE (mV)
SMPS2 PRESET 1.5V VOLTAGE DISTRIBUTION
MAX17007A/8 toc16
COMBINED-MODE CURRENT BALANCE vs. LOAD CURRENT
MAX17007A/8 toc17
SOFT-START WAVEFORM
MAX17007A/8 toc18
30 25 SAMPLE PERCENTAGE (%) 20 15 10 5 0 1.495 TA = +85C TA = +25C SAMPLE SIZE = 100
50
5V 0 2V 0 1.05V 1.5V 0 0 5V A B C D E F
40 VCSH - VCSL (mV)
30
20
10 SMPS1 SMPS2 0 1.497 1.499 1.501 1.503 1.505 0 5 10 15 20 25 30
0 5V 0 400s/div A. EN1, EN2, 5V/div B. REF, 2V/div C. VOUT1, 1V/div D. VOUT2, 1V/div E. PGOOD1, 5V/div F. PGOOD2, 5V/div
SMPS2 VOLTAGE (mV)
LOAD CURRENT (A)
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VDD = 5V, SKIP = GND, TA = +25C, unless otherwise noted.) SMPS1 STARTUP WAVEFORM SMPS1 STARTUP WAVEFORM (HEAVY LOAD) (LIGHT LOAD)
MAX17007A/8 toc19 MAX17007A/8 toc20
SMPS1 SHUTDOWN WAVEFORM
MAX17007A/8 toc21
5V 0 2V 0 1.05V 0 8A 5V 0 12V 0 5V 0 IOUT1 = 8A
A B C
5V 0 2V 0 1.05V IOUT1 = 2A 0 2A 0 5V 0 12V 0 5V 0
A B C
5V 0 2V 1.05V
A B C
0 D SKIP = 5V E F G 200s/div A. EN1, 5V/div E. PGOOD1, 10V/div B. REF, 2V/div F. LX1, 10V/div C. VOUT1, 500mV/div G. DL1, 10V/div D. ILX1, 5A/div 0 5V 0 12V 0 5V 0 D E IOUT1 = 0.5A SKIP = GND F G 200s/div A. EN1, 5V/div E. PGOOD1, 10V/div B. REF, 5V/div F. LX1, 10V/div C. VOUT1, 500mV/div G. DL1, 10V/div D. ILX1, 5A/div
D E F G 200s/div A. EN1, 5V/div E. PGOOD1, 10V/div B. REF, 2V/div F. LX1, 10V/div C. VOUT1, 500mV/div G. DL1, 10V/div D. ILX1, 10A/div
SMPS2 LOAD-TRANSIENT RESPONSE (PWM MODE)
MAX17007A/8 toc22
SMPS2 LOAD-TRANSIENT RESPONSE (SKIP MODE)
MAX17007A/8 toc23
SMPS1 OUTPUT OVERLOAD WAVEFORM
MAX17007A/8 toc24
1.05V 1.5V IOUT2 = 2A TO 10A TO 2A SKIP = 5V B 2A 12V C 0 20s/div A. VOUT2, 50mV/div B. ILX2, 10A/div C. LX2, 10V/div A. VOUT2, 50mV/div B. ILX2, 10A/div 0 20s/div C. LX2, 10V/div 0A 12V C A 1.5V IOUT2 = 0.5A TO 8.5A TO 0.5A SKIP = GND B A A 10A 2A 12V C 0 5V 0 5V 0 200s/div A. VOUT1, 500mV/div D. PGOOD1, 5V/div B. ILX1, 10A/div E. DL1, 5V/div C. LX1, 10V/div IOUT1 = 2A TO 15A D E B
10A
8A
SMPS1 OUTPUT OVERVOLTAGE WAVEFORM
MAX17007A/8 toc25
1.05V A 0 5V 0 5V 0 C B
40s/div A. VOUT1, 1V/div B. PGOOD1, 5V/div C. DL1, 5V/div
10
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VDD = 5V, SKIP = GND, TA = +25C, unless otherwise noted.)
DYNAMIC OUTPUT VOLTAGE TRANSITION (PWM MODE)
MAX17007A/8 toc26
MAX17007A/MAX17008
DYNAMIC OUTPUT VOLTAGE TRANSITION (SKIP MODE)
MAX17007A/8 toc27
DYNAMIC OUTPUT-VOLTAGE TRANSITION (SKIP MODE-FORCED TRANSITION)
MAX17007A/8 toc28
1.2V
IOUT1 = 2A A
1.2V A 1V
1.2V
IOUT1 = 3A A
1V 2A 12V 0 5V D 0 SKIP = 5V C REFIN1 = 1V TO 1.2V TO 1V B
1V IOUT1 = 1A B 0 REFIN1 = 1V TO 1.2V TO 1V C 12V 0 5V D 0 40s/div A. VOUT1, 100mV/div B. ILX1, 10A/div C. LX1, 10V/div D. DL1, 5V/div 20s/div A. VOUT1, 100mV/div B. ILX2, 10A/div IOUT1 = 1A REFIN1 = 1V TO 1.2V TO 1V SKIP = REF C. LX1, 10V/div D. DL1, 5V/div B
0 12V 0 5V 0
C
SKIP = GND
D
20s/div A. VOUT1, 100mV/div B. ILX1, 10A/div C. LX1, 10V/div D. DL1, 5V/div
Pin Description
PIN NAME FUNCTION 2V Reference Voltage Output. Bypass REF to GND with a 2.2nF ceramic capacitor. The reference can source up to 100A. Loading REF degrades output-voltage accuracy according to the REF load regulation error (see theTypical Operating Characteristics). The reference shuts down when both EN1 and EN2 are low. This four-level input determines the CSH1 to CSL1 current limit for SMPS1: VCC (5V) = 60mV current limit Open (3.3V) = 45mV current limit REF (2V) = 30mV current limit GND = 15mV current limit In combined mode, ILIM1 sets the current-limit threshold for both sides. This four-level input determines the CSH2 to CSL2 current limit for SMPS2: VCC (5V) = 60mV current limit Open (3.3V) = 45mV current limit REF (2V) = 30mV current limit GND = 15mV current limit In combined mode, ILIM2 is the current balance integrator (CCI) output pin. Connect a capacitor (CCCI) between CCI and the output. The CCI capacitor value depends on the ILIM1 setting based on the following table: ILIM1 VCC (5V) Open (3.3V) REF (2V) GND 4 VCC 5V Analog Supply Input. Bypass VCC from VDD using a 10 1F ceramic capacitor. CCCI at ILIM2 (pF) 120 180 220 470 resistor, and to analog ground using a
1
REF
2
ILIM1
3
ILIM2 (CCI)
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11
Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
Pin Description (continued)
PIN NAME FUNCTION Pulse-Skipping Control Input. This four-level input determines the mode of operation under normal steady-state conditions and dynamic output-voltage transitions: VDD (5V) = Forced-PWM operation Open (3.3V) = Ultrasonic mode (without forced-PWM during transitions) REF (2V) = Pulse-skipping mode (with forced-PWM during transitions) GND = Pulse-skipping mode (without forced-PWM during transitions) There are no dynamic transitions for SMPS2, so SKIP = 2V and SKIP = GND have the same pulseskipping behavior for SMPS2 without any forced-PWM transitions. In combined mode, the ultrasonic mode is disabled, and the SKIP = OPEN (3.3V) setting is identical to the SKIP = GND setting. Frequency-Setting Input for SMPS1. An external resistor between the input power source and TON1 sets the switching period (TSW1) of SMPS1: T SW1 = CTON (RTON1 + 6.5k ) where CTON = 16.26pF. TON1 is high impedance in shutdown. In combined mode, TON1 sets the switching period for both SMPS1 and SMPS2. Frequency-Setting Input for SMPS2. An external resistor between the input power source and TON2 sets the switching period (TSW2) of SMPS2: T SW2 = CTON (RTON2 + 6.5k ) where CTON = 16.26pF. Set TON2 to a switching frequency different from TON1. A 10% to 30% difference in switching frequency between SMPS1 and SMPS2 is recommended. TON2 is high impedance in shutdown. In combined mode, TON2 may be left open. External Reference Input for SMPS1. REFIN1 sets the feedback regulation voltage of CSL1. SMPS1 includes an internal window comparator to detect REFIN1 voltage changes that are greater than 50mV (typ), allowing the controller to blank PGOOD1 and the fault protection, and force the output transition, if enabled. When REFIN1 is tied to VCC, SMPS1 regulates the output to 1.05V. In combined mode, REFIN1 sets the feedback regulation voltage of the combined output. Output-Sense and Negative Current-Sense Input for SMPS1. When using the internal preset 1.05V feedback divider (REFIN1 = VCC), the controller uses CSL1 to sense the output voltage. Connect to the negative terminal of the current-sense element. Figure 14 describes two different currentsensing options--using accurate sense resistors or lossless inductor DCR sensing. Positive Current-Sense Input for SMPS1. Connect to the positive terminal of the current-sense element. Figure 14 describes two different current-sensing options--using accurate sense resistors or lossless inductor DCR sensing. Enable Control Input for SMPS1. Connect to VCC for normal operation. Pull EN1 low to disable SMPS1. The controller slowly ramps down the output voltage to ground and after the target voltage reaches 0.1V, the controller forces DL1 low. When both EN1 and EN2 are low, the device enters the low-power shutdown state. In combined mode, EN1 controls the combined SMPS output. EN2 is unused and must be grounded. Open-Drain Power-Good Output for SMPS1. PGOOD1 is low when the SMPS1 voltage is more than 200mV below or 300mV above the target voltage, during soft-start, and in shutdown. After the SMPS1 soft-start circuit has terminated, PGOOD1 becomes high impedance 200s after the output is in regulation. PGOOD1 is blanked (forced high-impedance state) when a dynamic REFIN1 transition is detected. High-Side Gate-Driver Output for SMPS1. DH1 swings from LX1 to BST1. DH1 is low in shutdown.
5
SKIP
6
TON1
7
TON2
8
REFIN1
9
CSL1
10
CSH1
11
EN1
12
PGOOD1
13
DH1
12
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers
Pin Description (continued)
PIN 14 15 16 17 NAME LX1 BST1 GND DL1 FUNCTION Inductor Connection for SMPS1. Connect LX1 to the switched side of the inductor. LX1 serves as the lower supply rail for the DH1 high-side gate driver. Bootstrap Capacitor Connection for SMPS1. The MAX17007A/MAX17008 include an internal boost switch/diode connected between VDD and BST1. Connect to an external capacitor as shown in Figure 1. Ground. Analog and power ground connection for the low-side gate driver of SMPS1. Low-Side Gate Driver Output for SMPS1. DL1 swings from GND to VDD. DL1 is forced low after the shutdown sequence has completed. DL1 is also forced high when an output overvoltage fault is detected, overriding any negative current-limit condition that may be present. DL1 is forced low in VCC UVLO. 5V Driver Supply Input. Connect VDD to VCC through a 10 resistor. Bypass to ground through a 2.2F or greater ceramic capacitor. VDD is internally connected to the BST diodes and the low-side gate drivers. Low-Side Gate-Driver Output for SMPS2. DL2 swings from PGND to VDD. DL2 is forced low after the shutdown sequence has completed. DL2 is also forced high when an output overvoltage fault is detected, overriding any negative current-limit condition that may be present. DL2 is forced low in VCC UVLO. Power Ground for the Low-Side Gate Driver of SMPS2 Bootstrap Capacitor Connection for SMPS2. The MAX17007A/MAX17008 include an internal boost switch/ diode connected between VDD and BST2. Connect to an external capacitor as shown in Figure 1. Inductor Connection for SMPS2. Connect LX2 to the switched side of the inductor. LX2 serves as the lower supply rail for the DH2 high-side gate driver. High-Side Gate-Driver Output for SMPS2. DH2 swings from LX2 to BST2. DH2 is low in shutdown. Open-Drain Power-Good Output for SMPS2. PGOOD2 is low when the FB2 voltage is more than 100mV below or 150mV above the target voltage, during soft-start, and in shutdown. After the SMPS2 soft-start circuit has terminated, PGOOD2 becomes high impedance 200s after the output is in regulation. In combined mode, PGOOD2 is not used and can be left open. SMPS2 Enable Input. Connect to VCC for normal operation. Pull EN2 low to disable SMPS2. The controller slowly ramps down the output voltage to ground, and after the target voltage reaches 0.1V, the controller forces DL2 low. When both EN1 and EN2 are low, the device enters the low-power shutdown state. In combined mode, EN2 is not used and should be connected to GND. Positive Current-Sense Input for SMPS2. Connect to the positive terminal of the current-sense element. Figure 14 describes two different current-sensing options--using accurate sense resistors or lossless inductor DCR sensing. Output-Sense and Negative Current-Sense Input for SMPS2. When using the internal preset 1.5V feedback divider (FB2 = REF), the controller uses CSL2 to sense the output voltage. Connect to the negative terminal of the current-sense element. Figure 14 describes two different current-sensing options--using accurate sense resistors or lossless inductor DCR sensing. SMPS2 Feedback Input. Adjust the SMPS2 voltage with a resistive voltage-divider between SMPS2 output and GND. Connect FB2 to REF for preset 1.5V output. Tie FB2 to VCC to configure the MAX17007A/MAX17008 for combined-mode operation. Exposed Backside Pad. Connect to analog ground.
MAX17007A/MAX17008
18
VDD
19
DL2
20 21 22 23
PGND BST2 LX2 DH2
24
PGOOD2
25
EN2
26
CSH2
27
CSL2
28 --
FB2 EP
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13
Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
+5V CVCC 1F 16 AGND ILIM1 ILIM2 VCC OPEN REF GND CURRENT LIMIT 60mV 45mV 30mV 15mV REF 2 ILIM1 4 VCC GND R9 10 18 VDD TON1 TON2 BST1 CVDD 2.2F PWR RTON1 220k
POWER GROUND
6 7 15
ANALOG GROUND RTON2 180k CBST1 0.1F NH1 CIN1 PWR
VIN 7V TO 20V L1 1H, 16A, 3m R3 1.5k R4 3.01k RNTC1 10k VOUT1 1.2V/1.0V, 12A COUT1 2 x 330F 12m PWR COUT1-CER 5 x 10F CERAMIC PWR
MAX17007A MAX17008
REF 3 ILIM2 (CCI) SKIP EN1 EN2
DH1 LX1 DL1
13 14 17 20 10 9 21
DL1 NL1 PWR C1 0.22F C2 1nF AGND CBST2 0.1F NH2 R7 10
4-LEVEL SKIP PIN
5 11 25
PGND CSH1 CSL1 BST2
CREF 2.2nF
1
REF
RREFIN1 = 80.6k RREFIN2 = 121k RREFIN3 = 249k H = 1.0V L = 1.2V
RREFIN1 RREFIN3
VIN 7V TO 20V CIN2 PWR L2 1H, 16A, 3m R5 1.5k R6 3.01k RNTC2 10k VOUT2 1.5V, 12A COUT2 2 x 330F 12m PWR COUT2-CER 5 x 10F CERAMIC PWR
8
DH2 REFIN1 LX2 DL2
23 22 19
RREFIN2
DL2 NL2
+3.3V R1 100k TO SYSTEM POWER-GOOD R2 100k 12 24 PGOOD1 PGOOD2 EP AGND
CSH2 CSL2
26 27 C3 0.22F C4 1nF 28
PWR
R8 10
FB2
AGND CONNECT TO REF FOR REF FIXED 1.5V OUTPUT
PWR
*LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE.
Figure 1. MAX17007A/MAX17008 Separate-Mode Standard Application Circuit
14
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers
Table 1. Component Selection for Standard Applications
COMPONENT V OUT1 = 1.0V/1.2V AT 12A (FIGURE 1) VIN = 7V to 20V TON1 = 220k (270kHz) (2x) 10F, 25V Taiyo Yuden TMK432BJ106KM (2x) 330F, 2.5V, 12m , C case SANYO 2R5TPE330MCC2 1H, 3.25m , 16A Wurth Electronics 7443552100 2A, 30V Schottky diode (SMA) Nihon EC21QS03L Central Semiconductor CMSH2-40M Fairchild Semiconductor (1x) FDS8690 8.6m /11.4m (typ/max) Fairchild Semiconductor (1x) FDS8670 4.2m /5m (typ/max) V OUT = 1.5V AT 12A (FIGURE 1) VIN = 7V to 20V TON2 = 180k (330kHz) (2x) 10F, 25V Taiyo Yuden TMK432BJ106KM (2x) 330F, 2.5V, 12m , C case SANYO 2R5TPE330MCC2 1H, 3.25m , 16A Wurth Electronics 7443552100 2A, 30V Schottky diode (SMA) Nihon EC21QS03L Central Semiconductor CMSH2-40M Fairchild Semiconductor (1x) FDS8690 8.6m /11.4m (typ/max) Fairchild Semiconductor (1x) FDS8670 4.2m /5m (typ/max)
MAX17007A/MAX17008
Input Capacitor (per Phase) Output Capacitor Inductor
Schottky Diode
High-Side MOSFET
Low-Side MOSFET
Table 2. Component Suppliers
MANUFACTURER AVX Corp. BI Technologies Fairchild Semiconductor International Rectifier KEMET Corp. NEC TOKIN America, Inc. Panasonic Corp. WEBSITE www.avxcorp.com www.bitechnologies.com www.fairchildsemi.com www.irf.com www.kemet.com www.nec-tokinamerica.com www.panasonic.com MANUFACTURER Pulse Engineering Renesas Technology Corp. Siliconix (Vishay) Sumida Corp. Taiyo Yuden TDK Corp. TOKO America, Inc. WEBSITE www.pulseeng.com www.renesas.com www.vishay.com www.sumida.com www.t-yuden.com www.component.tdk.com www.tokoam.com
Central Semiconductor Corp. www.centralsemi.com
SANYO Electric Company, Ltd. www.sanyodevice.com
Detailed Description
The MAX17007A/MAX17008 standard application circuit (Figure 1) generates the 1V to 1.2V/12A and 1.5V/12A chipset voltages in a notebook computer. The input supply range is 7V to 20V for the specific application. Table 1 lists component selections, while Table 2 lists the component manufacturers. Figure 2 shows the combinedmode standard application circuit and Figure 3 is the MAX17007A/MAX17008 functional diagram. The MAX17007A/MAX17008 contain two constant ontime step-down controllers designed for low-voltage power supplies. The two SMPSs can also be combined to operate as a two-phase high-current single-output regulator. Constant on-time Quick-PWM operation provides fast response to load transients and handles wide
I/O voltage ratios with ease, while maintaining a relatively constant switching frequency. The switching frequency can be adjusted between 200kHz and 600kHz with external resistors. Differential output current sensing allows output sense-resistor sensing for an accurate current-limit, lossless inductor DCR current sensing for lower power dissipation while maintaining 0.7% output accuracy. Overvoltage (MAX17007A) and undervoltage protection and accurate user-selectable current limits (four different levels) ensure robust operations. The MAX17007A/MAX17008 feature a special combined-mode configuration that allows higher current outputs to be supported. A current-balance integrator maintains equal currents in the two phases, improving efficiency and power distribution.
15
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
+5V CVCC 1F 16 AGND ILIM CURRENT CCCI (pF) LIMIT PIN VCC OPEN REF GND 60mV 45mV 30mV 15mV 120 180 220 470 REF 2 ILIM1 4 VCC GND R9 10 18 VDD TON1 TON2 BST1 CVDD 2.2F PWR 6 7 15 CBST1 0.1F NH1 VIN 7V TO 20V CIN1 PWR L1 1H, 16A, 3m R3 1.5k R4 3.01k RNTC1 10k VOUT1 1.2V/1.0V, 24A R7 10 VIN 7V TO 20V CIN2 PWR L2 1H, 16A, 3m R5 1.5k R6 3.01k RNTC2 10k COUT1 4 x 330F 12m PWR COUT1-CER 10 x 10F CERAMIC PWR X RTON1 220k ANALOG GROUND POWER GROUND
MAX17007A MAX17008
CCCI 220pF
DH1 LX1
13 14 17 20 10 9 21
ILIM2 FUNCTIONS AS V OUT CCI OUTPUT IN COMBINED MODE
3 5
ILIM2 (CCI) SKIP EN1 EN2 REF
DL1 PGND CSH1 CSL1 BST2
DL1 NL1 PWR C1 0.22F C2 1nF AGND CBST2 0.1F NH2
11 EN2 MUST BE GROUNDED CREF 2.2nF 25 1
RREFIN1 = 80.6k RREFIN2 = 121k RREFIN3 = 249k H = 1.0V L = 1.2V
RREFIN1 RREFIN3
8
DH2 REFIN1 LX2 DL2
23 22 19
RREFIN2
DL2 NL2
+3.3V R1 100k 12 PGOOD2 NOT USED IIN COMBINED MODE 24 PGOOD1 PGOOD2 EP AGND
CSH2 CSL2
26 27 C3 0.22F C4 1nF 28
PWR
R8 10
FB2
AGND +5V CONNECT TO 5V FOR COMBINED MODE OPERATION
PWR
*LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE.
Figure 2. MAX17007A/MAX17008 Combined-Mode Standard Application Circuit
16
______________________________________________________________________________________
Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
CURRENT BALANCE Gm TON2 TON1 SKIP ILIM1 CSH1 CSL1 CURRENT LIMIT 1 (FIGURE 8) CURRENT LIMIT 2 (FIGURE 8) COMBINE (FB2 = VCC) COMBINE (FB2 = VCC) ILIM2 CSH2 CSL2 Gm
CURRENTSENSE GAIN Gm BST1 DH1 LX1 VDD DL1 GND CSL1 EN1 TARGET1 REFIN1 VCC REF 2.0V REF
VALLEY CURRENT LIMIT
VALLEY COMBINE CURRENT (FB2 = VCC) LIMIT
CURRENTSENSE GAIN Gm BST2 DH2 LX2
PWM CONTROLLER 1 (FIGURE 4)
MUX
PWM CONTROLLER 2 (FIGURE 4)
VDD DL2 PGND COMBINE (FB2 = VCC) CSL2
FAULT1
FAULT2
MUX
TARGET2
EN2
SMPS1 TARGET DECODE (FIGURE 9A)
SMPS2 TARGET DECODE (FIGURE 9B)
FB2
PGOOD1
POWER-GOOD AND FAULT PROTECTION 1 (FIGURE 13)
POWER-GOOD AND FAULT PROTECTION 2 (FIGURE 13)
MAX17007A MAX17008
PGOOD2
Figure 3. MAX17007A/MAX17008 Functional Diagram
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17
Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
+5V Bias Supply (VCC, VDD) The MAX17007A/MAX17008 require an external 5V bias supply in addition to the battery. Typically, this 5V bias supply is the notebook's 95%-efficient 5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the 5V supply can be generated with an external linear regulator such as the MAX1615. The 5V bias supply powers both the PWM controllers and internal gate-drive power, so the maximum current drawn depends on the external MOSFET's gate capacitance, and the selected switching frequency:
IBIAS = IQ + fSW1QG(SMPS1) + fSW2QG(SMPS2) = 4mA to 40mA (typ) Bypass VCC with a 1F or greater ceramic capacitor to the analog ground. Bypass VDD with a 2.2F or greater ceramic capacitor to the power ground. VCC and VDD should be separated with a 10 resistor (Figure 1).
2V Reference
The 2V reference is accurate to 1% over temperature and load, making REF useful as a precision system reference. Bypass REF to GND with a 2.2nF. The reference sources up to 100A and sinks 10A to support external loads.
Combined-Mode Operation (FB2 = VCC) Combined-mode operation allows the MAX17007A/ MAX17008 to support even higher output currents by sharing the load current between two phases, distributing the power dissipation over several power components to improve the efficiency. The MAX17007A/ MAX17008 are configured in combined mode by connecting FB2 to VCC. See Figure 2 for the combinedmode standard application circuit. Table 3 lists the pin function differences between combined mode and separate mode. See the Pin Description for additional details.
Table 3. Pin Function in Combined and Separate Modes
PIN FB2 REFIN1 EN1 EN2 PGOOD1 PGOOD2 TON1 TON2 ILIM1 ILIM2 (CCI) SKIP COMBINED MODE Connect to VCC to configure MAX17007A/MAX17008 for combined-mode operation SEPARATE MODE Connect to REF for preset 1.5V, or use a resistordivider to set the SMPS2 output voltage
Sets the combined output voltage--dynamic, fixed, and Sets the SMPS1 output voltage--dynamic, fixed, preset voltages supported and preset voltages supported Enables/disables combined output Not used; connect to GND Power-good indicator for combined output voltage Not used; can be left open Sets the per-phase switching frequency for both SMPSs Not used; leave open Sets the per-phase current limit for both SMPSs Current-balance integrator output; connect a capacitor from CCI to the output Enables/disables SMPS1 Enables/disables SMPS2 Power-good indicator for SMPS1 Power-good indicator for SMPS2 Sets the switching frequency for SMPS1 Sets the switching frequency for SMPS2 Sets SMPS1 current limit Sets SMPS2 current limit
Only three distinct modes of operation; ultrasonic mode Supports all four modes of operation not supported
18
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
SMPS Detailed Description
Free-Running Constant-On-Time PWM Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time, current-mode regulator with voltage feed-forward. This architecture relies on the output filter capacitor's ESR to act as a currentsense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a oneshot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. Another one-shot sets a minimum off-time (150ns typ). The on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the valley current-limit threshold, and the minimum off-time oneshot has timed out. Figure 4 is the PWM controller block diagram.
On-Time One-Shot
The heart of the PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. In independent mode, the high-side switch on-time is inversely proportional to the battery voltage as sensed by the TON1 and TON2 inputs, and proportional to the voltages on CSL1 and CSL2 pins: SMPS1 On-Time tON1 = TSW1 (VCSL1/VIN) SMPS2 On-Time tON2 = TSW2 (VCSL2/VIN) where TSW1 (switching period of SMPS1) is set by the resistance between TON1 and VIN, TSW2 is set by the resistance between TON2 and V IN . This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator.
TON ON-TIME COMPUTE CSL OR CCI Q
tOFF(MIN) TRIG
MAX17007A MAX17008
tON TRIG ONE-SHOT ERROR AMPLIFIER SLOPE COMP INTEGRATOR (CCV) Q
S R
Q
DH DRIVER
S Q TARGET R VALLEY CURRENT LIMIT ZERO CROSSING DL DRIVER
AMPLIFIED CURRENT SENSE
INTERNAL FB
OV FAULT
Figure 4. PWM Controller Block Diagram
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19
Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
Switching Frequency The MAX17007A/MAX17008 feature independent resistor-programmable switching frequencies for each SMPS, providing flexibility for applications where one SMPS operates at a lower switching frequency when connected to a high-voltage input rail while the other SMPS operates at a higher switching frequency when connected to a lower voltage rail as a second-stage regulator. Connect a resistor (RTON) between TON and VIN to set the switching period TSW = 1/fSW: TSW1 = CTON (RTON1 + 6.5k)
TSW2 = CTON (RTON2 + 6.5k) where CTON = 16.26pF. A 97.5k to 302.5k corresponds to switching periods of 1.67s (600kHz) to 5s (200kHz) for SMPS1 and SMPS2. High-frequency (600kHz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This may be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. Low-frequency (200kHz) operation offers the best overall efficiency at the expense of component size and board space. For continuous conduction operation, the actual switching frequency can be estimated by: fSW = VOUT + VDIS t ON (VIN + VCHG )
Combined-Mode Current Balance In combined mode, the one-shot for SMPS2 varies the on-time in response to the input voltage and the difference between the SMPS1 and SMPS2 inductor currents. The SMPS1 one-shot in combined mode behaves the same way as it does in separate mode. As such, SMPS2 regulates the current balance, while SMPS1 regulates the voltage.
Two identical transconductance amplifiers integrate the difference between SMPS1 and SMPS2 current-sense signals. The summed output is internally connected to CCI, allowing adjustment of the integration time constant with a compensation network (usually a capacitor) connected between CCI and the output. The resulting compensation current and voltage are determined by the following equations: ICCI = Gm[(VCSH1 - VCSL1) - (VCSH2 - VCSL2)] VCCI = VOUT + ICCIZCCI where ZCCI is the impedance at the CCI output. The SMPS2 on-time one-shot uses this integrated signal (VCCI) to set the SMPS2 high-side MOSFETs on-time. When SMPS1 and SMPS2 current-sense signals (VCSH1 - VCSL1 and VCSH2 - VCSL2) become unbalanced, the transconductance amplifiers adjust the SMPS2 on-time, which increases or decreases the SMPS2 inductor current until the current-sense signals are properly balanced. In combined mode, the SMPS2 on-time is given by: SMPS2 On-Time tON2 = TSW2 (VCCI/VIN)
where VDIS is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and printed-circuit board (PCB) resistances; V CHG is the sum of the resistances in the charging path, including the high-side switch, inductor, and PCB resistances; and tON is the on-time calculated by the on-time block. When operating in separate mode, it is recommended that both SMPS switching frequencies be set apart by 10% to 30% to prevent the two sides from beating against each other.
SMPS Enable Controls (EN1, EN2)
EN1 and EN2 provide independent control of output soft-start and soft-shutdown. This allows flexible control of startup and shutdown sequencing. The outputs can be started simultaneously, sequentially, or independently. To provide sequential startup, connect EN of one regulator to PGOOD of the other. For example, with EN1 connected to PGOOD2, OUT1 soft-starts after OUT2 is in regulation. When configured in separate mode, the two outputs are independent. A fault at one output does not trigger shutdown of the other. When configured in combined mode (FB2 = VCC), EN1 is the master control input that enables/disables the combined output, while EN2 has no function and must be connected to GND. The startup slew rate follows that of SMPS1. Toggle EN low to clear the overvoltage, undervoltage, and thermal-fault latches.
Combined-Mode On-Time One-Shot In combined mode (FB2 = VCC), TON1 sets the ontime, and hence the switching frequency, for both SMPS. The on-time is programmed using the TON1 equation, which sets the switching frequency per phase. The effective switching frequency as seen on the input and output capacitors is twice the per-phase frequency.
20
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers
Soft-Start Soft-start begins when EN is driven high and REF is in regulation. During soft-start, the output is ramped up from 0V to the final set voltage at 1.3mV/s slew rate for SMPS1, and 0.65mV/s for SMPS2, reducing the inrush current and providing a predictable ramp-up time for power sequencing: V V tSTART1 = tSHDN1 = REFIN1 = REFIN1 SRSS1 1.3mV / s
tSTART2 = tSHDN2 = VFB2 VFB2 = SRSS2 0.65mV / s response). This eliminates the need for the Schottky diode normally connected between the output and ground to clamp the negative output-voltage excursion.
MAX17007A/MAX17008
Modes of Operation
S Forced-PWM Mode (SKIP = 5V) The low-noise forced-PWM mode (SKIP = 5V) disables the zero-crossing comparator, which controls the lowside switch on-time. This forces the low-side gate-drive waveform to constantly be the complement of the highside gate-drive waveform, so the inductor current reverses at light loads while DH maintains a duty factor of VOUT/VIN. The benefit of forced-PWM mode is to keep the switching frequency fairly constant. However, forced-PWM operation comes at a cost: the no-load 5V bias current remains between 2mA to 5mA, depending on the switching frequency. The MAX17007A/MAX17008 automatically use forcedPWM operation during shutdown, regardless of the SKIP configuration.
The soft-start circuitry does not use a variable current limit, so full output current is available immediately. The respective PGOOD becomes high impedance approximately 200s after the target voltage has been reached. The MAX17007A/MAX17008 automatically use pulse-skipping mode during soft-start and use forced-PWM mode during soft-shutdown, regardless of the SKIP configuration. For automatic startup, the battery voltage should be present before VCC. If the controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. The controller remains shut down until the fault latch is cleared by toggling EN or cycling the VCC power supply below 0.5V.
Soft-Shutdown Soft-shutdown begins when the system pulls EN low, an output undervoltage fault, or a thermal fault. During soft-shutdown, the respective PGOOD is pulled low immediately and the output voltage ramps down with the same startup slew rate for the respective outputs. After the controller reaches the 0V target, the drivers are disabled (DL_ and DH_ pulled low) and the internal 10 discharge on CSL_ activated. The MAX17007A/ MAX17008 shut down completely when both EN are low--the reference turns off after both SMPSs have reached the 0V target, and the supply current drops to about 1A (max). Slowly discharging the output capacitors by slewing the output over a long period of time (typically 0.5ms to 2ms) keeps the average negative inductor current low (damped response), thereby preventing the negative output-voltage excursion that occurs when the controller discharges the output quickly by permanently turning on the low-side MOSFET (underdamped
Automatic Pulse-Skipping Mode S (SKIP = GND or 2V) In skip mode (SKIP = GND or 2V), an inherent automatic switchover to PFM takes place at light loads. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The zero-crossing comparator threshold is set by the differential across CSL_ and CSH_. DC output-accuracy specifications refer to the threshold of the error comparator. When the inductor is in continuous conduction, the MAX17007A/MAX17008 regulate the valley of the output ripple, so the actual DC output voltage is higher than the trip level by 50% of the output ripple voltage. In discontinuous conduction (SKIP = GND or 2V and IOUT < ILOAD(SKIP)), the output voltage has a DC regulation level higher than the error-comparator threshold by approximately 1.5% due to slope compensation. However, the internal integrator corrects for most of it, resulting in very little load regulation. When SKIP = 2V, the MAX17007A/MAX17008 use forcedPWM operation during all dynamic output-voltage transitions until 100s after the transition has been completed--REFIN1 and the internal target are within 50mV (typ) and an error-amplifier transition is detected. Since SMPS2 does not support dynamic transitions, SKIP = 2V and SKIP = GND have the same pulse-skipping behavior without any forced-PWM transitions.
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
When SKIP is pulled to GND, the MAX17007A/MAX17008 remain in pulse-skipping mode. Since the output is not able to sink current, the timing for negative dynamic output-voltage transitions depends on the load current and output capacitance. Letting the output voltage drift down is typically recommended in order to reduce the potential for audible noise since this eliminates the input current surge during negative output-voltage transitions. Figure 5 shows the pulse-skipping/discontinuous crossover point. S Ultrasonic Mode (SKIP = Open = 3.3V) Leaving SKIP unconnected or connecting SKIP to 3.3V activates a unique pulse-skipping mode with a minimum switching frequency of 25kHz. This ultrasonic pulse-skipping mode eliminates audio-frequency modulation that would otherwise be present when a lightly loaded controller automatically skips pulses. In ultrasonic mode, the controller automatically transitions to fixed-frequency PWM operation when the load reaches the same critical conduction point (ILOAD(SKIP)) that occurs when normally pulse skipping. An ultrasonic pulse occurs when the controller detects that no switching has occurred within the last 30s. Once triggered, the ultrasonic controller pulls DL high, turning on the low-side MOSFET to induce a negative inductor current (Figure 6). After the inductor current reaches the negative ultrasonic current threshold, the controller turns off the low-side MOSFET (DL pulled low) and triggers a constant on-time (DH driven high). When the on-time has expired, the controller reenables the low-side MOSFET until the controller detects that the inductor current dropped below the zero-crossing threshold. Starting with a DL pulse greatly reduces the peak output voltage when compared to starting with a DH pulse. The output voltage at the beginning of the ultrasonic pulse determines the negative ultrasonic current threshold, resulting in the following equations for SMPS1: VISONIC1 = IL1R CS1 = ( VREFIN1 - VCSL1) x 0.65 (SMPS1 adjustable mode) VISONIC1 = I L1R CS1 = (1.05V - VCSL1) x 0.65 (SMPS1 preset mode) where VCSL1 > VREFIN1 in adjustable mode, VCSL1 > 1.05V in preset mode, and RCS1 is the current-sense resistance seen across CSH1 to CSL1. Similarly for SMPS2: VISONIC2 = IL2R CS2 = ( 0.7V - VFB2 ) x 0.65 (SMPS2 adjustable mode) VISONIC2 = I L2R CS2 = (1.5V - VCSL2 ) x 0.65 (SMPS2 preset mode) where VCSL2 > 0.7V in adjustable mode, VCSL2 > 1.5V in preset mode, and RCS2 is the current-sense resistance seen across CSH2 to CSL2. In combined mode, ultrasonic mode setting is disabled, and the SKIP = OPEN (3.3V) setting is identical to the SKIP = GND setting.
40s (MAX) INDUCTOR CURRENT
I t
=
VIN - VOUT L IPEAK
INDUCTOR CURRENT
ZERO-CROSSING DETECTION ILOAD = IPEAK/2
0 ISONIC
ON-TIME (tON)
0
ON-TIME
TIME
Figure 5. Pulse-Skipping/Discontinuous Crossover Point
22
Figure 6. Ultrasonic Waveform
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers
Valley Current-Limit Protection
The current-limit circuit employs a unique "valley" current-sensing algorithm that senses the inductor current across the output current-sense element--inductor DCR or current-sense resistor, which generates a voltage between CSH_ and CSL_. If the current exceeds the valley current-limit threshold during the low-side MOSFET conduction time, the PWM controller is not allowed to initiate a new cycle. The valley current-limit threshold is set by the four-level ILIM_ pin, with selectable limits of 15mV, 30mV, 45mV, and 60mV. The actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor ripple current (Figure 7). Therefore, the exact currentlimit characteristic and maximum load capability are a function of the inductor value and battery voltage. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. See Figure 8. In forced-PWM mode, the MAX17007A/MAX17008 also implement a negative current limit to prevent excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit. In combined mode, ILIM1 sets the per-phase current limit for both phases.
MAX17007A/MAX17008
MOSFET Gate Drivers (DH, DL)
The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications, where a large V IN VOUT differential exists. The high-side gate driver (DH) sources and sinks 1.2A, and the low-side gate driver (DL) sources 1.0A and sinks 2.4A. This ensures robust gate drive for high-current applications. The DH floating high-side MOSFET driver is powered by internal boost switch charge pumps at BST, while the DL synchronous-rectifier driver is powered directly by the 5V bias supply (VDD).
CURRENTSENSE GAIN
IPEAK
ILIM
QUAD-LEVEL DECODE
ILOAD INDUCTOR CURRENT
VALLEY CURRENT LIMIT
ILIMIT
CSH ZERO CROSSING CSL
ILIM(VAL) = ILOAD(MAX) 1-
( LIR ) 2
0
TIME SKIP
Figure 7. "Valley" Current-Limit Threshold Point
Figure 8. Current-Limit Block Diagram
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
Output Voltage
The MAX17007A/MAX17008 feature preset and adjustable output voltages for both SMPSs, and dynamic output voltages for SMPS1. In combined mode, the output voltage is set by REFIN1, and all features for SMPS1 output-voltage configuration and dynamic voltage changes apply to the combined output. Figure 9 is the SMPS target decode block diagram. voltage to preset 1.5V. The SMPS1 output voltage can be adjusted up to 2V by changing REFIN1 voltage without using an external resistive voltage-divider. The output voltage of SMPS2 can be adjusted with an external resistive voltage-divider between CSL2 and GND with the center tap connected to FB2 (Figure 10). Choose RFB2LO (resistance from FB2 to GND) to be approximately 10k and solve for R FB2HI (resistance from CSL2 to FB2) using the equation: V RFB2HI = RFB2LO CSL2 - 1 0.7V The MAX17007A/MAX17008 regulate the valley of the output ripple, so the actual DC output voltage is higher than the slope compensated target by 50% of the output ripple voltage. Under steady-state conditions, the MAX17007A/MAX17008s' internal integrator corrects for this 50% output ripple voltage error, resulting in an output-voltage accuracy that is dependent only on the offset voltage of the integrator amplifier provided in the Electrical Characteristics table.
Preset/Adjustable Output Voltages (Dual-Mode Feedback) Connect REFIN1 to VCC to set the SMPS1 voltage to preset 1.05V. Connect FB2 to REF to set the SMPS2
VCC - 1V PRESET (FB1 = VCC)
REFIN1
TARGET1
REF (2.0V) 9.5R
1.05V
10.5R (A) SMPS1 TARGET DECODE VCC - 1V
COMBINE (FB2 = VCC)
FB2 PRESET (FB2 = REF)
Dynamic Output Voltages (REFIN1) The MAX17007A/MAX17008 regulate the output to the voltage set at REFIN1. By changing the voltage at REFIN1 (Figure 11), the MAX17007A/MAX17008 can be used in applications that require dynamic output voltage changes between two set points. For a step-voltage change at REFIN1, the rate of change of the output voltage is limited either by the internal 9.5mV/s slewrate circuit or by the component selection--inductor current ramp, the total output capacitance, the current limit, and the load during the transition--whichever is slower. The total output capacitance determines how much current is needed to change the output voltage, while the inductor limits the current ramp rate.
L2 TARGET2 LX2 RSENSE2
REF - 0.3V TARGET1 REF (2.0V) 5R 1.5V
MAX17007A DL2 MAX17008
GND CSH2 8R CSL2 0.7V FB2
NL2
COUT2
RFB2HI 7R (B) SMPS2 TARGET DECODE RFB2LO
Figure 9. SMPS Target Decode Block Diagram
24
Figure 10. Setting VOUT2 with a Resistive Voltage-Divider
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers
Additional load current can slow down the output voltage change during a positive REFIN1 voltage change, and can speed up the output voltage change during a negative REFIN1 voltage change. blanks the UVP protection, and sets the OVP threshold to max REF +300mV. The blanking remains until 1) the internal target and REFIN1 are within 50mV of each other, and 2) an edge is detected on the error amplifier signifying that the output is in regulation. This prevents the system or internal fault protection from shutting down the controller during transitions. Figure 11 shows the dynamic REFIN1 transition (SKIP = GND) and Figure 12 shows the dynamic REFIN1 transition (SKIP = REF).
DYNAMIC REFIN1 WINDOW
MAX17007A/MAX17008
Automatic Fault Blanking (SMPS1) When the MAX17007A/MAX17008 detect that the internal target and REFIN1 are more than 50mV (typ) apart, the controller automatically blanks PGOOD1,
REFIN1
VOUT1
ACTUAL VOUT1
-50mV
INTERNAL TARGET1 INTERNAL PWM CONTROL NO PULSES: VOUT1 > VTARGET1 SKIP
LX1 PGOOD1 LOWER THRESHOLD + UVP1 PGOOD1 UPPER THRESHOLD + OVP1
BLANK HIGH-Z SET TO REF + 300mV
BLANK HIGH-Z TARGET1 + 300mV
Figure 11. Dynamic REFIN1 Transition (SKIP = GND)
DYNAMIC REFIN1 WINDOW
REFIN1
-50mV VOUT1 +50mV INTERNAL PWM CONTROL INTERNAL TARGET1 = ACTUAL VOUT1
PWM
SKIP
PWM
SKIP
LX1 PGOOD1 LOWER THRESHOLD + UVP1 PGOOD1 UPPER THRESHOLD + OVP1 BLANK HIGH-Z REF + 300mV 200s TARGET1 + 300mV BLANK HIGH-Z TARGET1 + 300mV 200s
Figure 12. Dynamic REFIN1 Transition (SKIP = REF)
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
Internal Integration An integrator amplifier forces the DC average of the FB voltage to equal the target voltage. This internal amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure 4), allowing accurate DC output-voltage regulation regardless of the compensated feedback ripple voltage and internal slopecompensation variation. The integrator amplifier has the ability to shift the output voltage by 140mV (typ). The MAX17007A/MAX17008 disable the integrator by connecting the amplifier inputs together at the beginning of all dynamic REFIN1 transitions done in pulseskipping mode. The integrator remains disabled until 20s after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator).
PGOOD1 goes low if the output voltage drops 200mV below the target voltage (REFIN1 or fixed 1.05V), or rises 300mV above the target voltage (REFIN1 or fixed 1.05V), or the SMPS1 controller is shut down. In adjustable mode, PGOOD2 goes low if the feedback voltage drops 100mV below the target voltage (0.7V), or rises 150mV above the target voltage (0.7V), or the SMPS2 controller is shut down. In preset mode (fixed 1.5V), the PGOOD2 thresholds are -200mV and +300mV. For a logic-level PGOOD output voltage, connect an external pullup resistor between PGOOD and VDD. A 100k pullup resistor works well in most applications. See Figure 13.
Power-Good Outputs (PGOOD) and Fault Protection
PGOOD_ is the open-drain output that continuously monitors the respective output voltage for undervoltage and overvoltage conditions. The respective PGOOD_ is actively held low in shutdown (EN_ = GND) during softstart and soft-shutdown. Approximately 200s (typ) after the soft-start terminates, PGOOD_ becomes high impedance as long as the respective output voltage is in regulation.
TARGET - VUVP
Overvoltage Protection (OVP, MAX17007A Only) When the internal feedback voltage rises above the overvoltage threshold, the OVP comparator immediately pulls DH low and forces DL high, pulls PGOOD low, sets the fault latch, and disables the faulted SMPS controller. Toggle EN or cycle VCC power below the VCC POR to clear the fault latch and restart the controller. The overvoltage thresholds are +300mV for SMPS1 (fixed 1.05V and adjustable REFIN1), +300mV for SMPS2 in preset mode (fixed 1.5V output), and +150mV for SMPS2 in adjustable mode (0.7V feedback). An OV fault on one side does not affect the other side.
TARGET + VOVP CSL OR FB
NOTE: ONLY THE MAX17007A HAS OVP FUNCTION ENABLED.
EN SOFT-START COMPLETE OVP UVP ONE SHOT 200s FAULT LATCH FAULT
OVP ENABLED (MAX17007A ONLY)
POWER-GOOD
IN CLK
OUT
Figure 13. Power-Good and Fault Protection
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers
Undervoltage Protection (UVP) When the feedback voltage drops below the undervoltage threshold, the controller immediately pulls PGOOD low and triggers a 200s one-shot timer. If the feedback voltage remains below the undervoltage fault threshold for the entire 200s, then the undervoltage fault latch of the faulted SMPS is set and that SMPS begins its shutdown sequence. When the internal target voltage drops below 0.1V, the MAX17007A/MAX17008 force DL low for the faulted SMPS. Toggle EN or cycle VCC power below VCC POR to clear the fault latch and restart the controller.
The undervoltage thresholds are -200mV for SMPS1 (fixed 1.05V and adjustable REFIN1), -200mV for SMPS2 in preset mode (fixed 1.5V output), and -100mV for SMPS2 in adjustable mode (0.7V feedback). A UV fault on one side does not affect the other side.
Thermal-Fault Protection (TSHDN) The MAX17007A/MAX17008 feature a thermal-fault protection circuit. When the junction temperature rises above +160C, a thermal sensor activates the fault latch, pulls PGOOD low, and shuts down the controller. Both DL and DH are pulled low. Toggle EN or cycle VCC power below VCC POR to reactivate the controller after the junction temperature cools by 15C.
VCC POR and UVLO Each SMPS of the MAX17007A/MAX17008 is enabled when its respective EN is driven high. On the first rising EN, the reference powers up first. Once the reference exceeds its undervoltage lockout (UVLO) threshold (~ 60s), the internal analog blocks are turned on and masked by a 140s one-shot delay in order to allow the bias circuitry and analog blocks enough time to settle to their proper states. With the control circuitry reliably powered up, the PWM controller begins switching. The second rising EN, if controlled separately, also has the 140s one-shot delay before its first DH pulse. Power-on reset (POR) occurs when VCC rises above approximately 3V, resetting the fault latch and preparing the controller for operation. The VCC UVLO circuitry inhibits switching until VCC rises above 4.25V. The controller powers up the reference once the system enables the controller, VCC exceeds 4.25V, and either EN is driven high. With the reference in regulation, the controller ramps the output voltage to the target voltage with a 1.3mV/s slew rate for SMPS1 and 0.65mV/s for SMPS2.
If the VCC voltage drops below 4.25V, the controller assumes that there is not enough supply voltage to make valid decisions. To protect the output from overvoltage faults, the controller shuts down immediately and forces a high-impedance output (DL and DH pulled low).
MAX17007A/MAX17008
Table 4. Fault Protection and Shutdown Operation
MODE Shutdown (EN_ = High to Low) Output UVP (Latched) Thermal Fault (Latched) Output OVP (Latched) CONTROLLER STATE Voltage soft-shutdown initiated. Error amplifier target slowly ramped down to GND. Controller shuts down and internal target slews down. Controller remains off until EN_ toggled or VCC power cycled. Controller shuts down and the internal target slews down. Controller remains off until VCC rises back above UVLO threshold. SMPS controller enabled (assuming EN_ pulled high). SMPS inactive. DRIVER STATE DL_ low and DH_ low after soft-shutdown completed, internal 10 discharge on CSL_ activated. (Target < 0.1V.) DL_ immediately forced high, DH_ pulled low (high-side MOSFET disabled). DL_ low, DH_ low, internal 10 discharge on CSL_ activated. DL_, DH_ switching. DL_ low.
VCC UVLO Falling Edge
VCC UVLO Rising Edge VCC POR
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
Quick-PWM Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: * Input voltage range: The maximum value (VIN(MAX)) must accommodate the worst-case input supply voltage allowed by the notebook's AC adapter voltage. The minimum value (V IN(MIN) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. * Maximum load current: There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Most notebook loads generally exhibit ILOAD = ILOAD(MAX) x 80%. Switching frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target due to rapid improvements in MOSFET technology that are making higher frequencies more practical. Inductor operating point: This choice provides trade-offs between size vs. efficiency and transient response vs. output noise. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. VOUT VIN - VOUT L= fSWILOAD(MAX)LIR VIN For example: ILOAD(MAX) = 15A, VIN = 12V, VOUT = 1.5V, fSW = 300kHz, 30% ripple current or LIR = 0.3: 12V - 1.5V 1.5V L= = 0.97H 300kHz x 15A x 0.3 12V Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): LIR IPEAK = ILOAD(MAX) 1+ 2 In combined mode, ILOAD(MAX) is the per-phase maximum current, which is half the actual maximum load current for the combined output.
Transient Response
The inductor ripple current impacts transient-response performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time. The worst-case output sag voltage can be determined by: L ILOAD(MAX) VSAG =
*
*
VIN - VOUT 2COUT VOUT TSW - tOFF(MIN) VIN
(
)2 VOUT TSW + tOFF(MIN) VIN
where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics table). The amount of overshoot due to stored inductor energy can be calculated as: VSOAR
(ILOAD(MAX) )2L
NPH 2COUT VOUT
Inductor Selection
The per-phase switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows:
28
where NPH is the number of active phases per output. NPH is 1 for separate mode, and NPH is 2 for combined-mode operation.
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers
Setting the Valley Current Limit
The minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the ripple current; therefore: ILIMIT(LOW) > ILOAD(MAX) LIR 1 NPH 2 For the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in Figure 14a. This configuration constantly monitors the inductor current, allowing accurate current-limit protection. However, the parasitic inductance of the current-sense resistor can cause current-limit inaccuracies, especially when using low-value inductors and current-sense resistors. This parasitic inductance (LESL) can be cancelled by adding an RC circuit across the sense resistor with an equivalent time constant: CEQREQ = LESL RSENSE
MAX17007A/MAX17008
where I LIMIT(LOW) equals the minimum current-limit threshold voltage divided by the output sense element (inductor DCR or sense resistor). The four-level ILIM setting sets a valley current limit of 15mV, 30mV, 45mV, or 60mV across the CSH_ to CSL_ differential input. Special attention must be made to the tolerance and thermal variation of the on-resistance in the case of DCR sensing. Use the worst-case maximum value for RDCR from the inductor data sheet, and add some margin for the rise in RDCR with temperature. A good general rule is to allow 0.5% additional resistance for each C of temperature rise, which must be included in the design margin unless the design includes an NTC thermistor in the DCR network to thermally compensate the current-limit threshold. The current-sense method (Figure 14) and magnitude determine the achievable current-limit accuracy and power loss. The sense resistor can be determined by: RSENSE_ = VLIM_/ILIMIT_
Alternatively, low-cost applications that do not require highly accurate current-limit protection can reduce the overall power dissipation by connecting a series RC circuit across the inductor (Figure 14b) with an equivalent time constant: RCS = and: RDCR = L 1 1 x + CEQ R1 R2 R2 RDCR R1+ R2
where RCS is the required current-sense resistance and RDCR is the inductor's series DC resistance. Use the worst-case inductance and RDCR values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load.
INPUT (VIN) DH_ LX_ NH CIN L SENSE RESISTOR LESL RSENSE CEQREQ = NL DL REQ CEQ COUT LESL RSENSE
MAX17007A MAX17008
DL_ PGND CSH_ CSL_
a) OUTPUT SERIES RESISTOR SENSING
Figure 14. Current-Sense Configurations (Sheet 1 of 2)
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
INPUT (VIN) DH_ LX_ NH CIN L INDUCTOR RDCR RCS = NL DL R1 R2 CEQ COUT L RDCR = C EQ 11 [ R1 + R2 ] R2 RDCR R1 + R2
MAX17007A DL_ MAX17008
PGND CSH_ CSL_ b) LOSSLESS INDUCTOR SENSING
FOR THERMAL COMPENSATION: R2 SHOULD CONSIST OF AN NTC RESISTOR IN SERIES WITH A STANDARD THIN-FILM RESISTOR.
Figure 14. Current-Sense Configurations (Sheet 2 of 2)
Output Capacitor Selection
The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. In core and chipset converters and other applications where the output is subject to large-load transients, the output capacitor's size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: (RESR + RPCB ) I VSTEP LOAD(MAX) In low-power applications, the output capacitor's size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor's ESR. The maximum ESR to meet ripple requirements is: VINfSWL RESR V VIN - VOUT ) VOUT RIPPLE ( where fSW is the switching frequency. With most chemistries (polymer, tantalum, aluminum, electrolytic), the actual capacitance value required relates to the physical size needed to achieve low ESR and the chemistry limits of the selected capacitor technology. Ceramic capacitors provide low ESR, but the capacitance and voltage rating (after derating) are determined by the capacity needed to prevent VSAG and VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the
30
rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). Thus, the output capacitor selection requires carefully balancing capacitor chemistry limitations (capacitance vs. ESR vs. voltage rating) and cost.
Output Capacitor Stability Considerations For Quick-PWM controllers, stability is determined by the in-phase feedback ripple relative to the switching frequency, which is typically dominated by the output ESR. The boundary of instability is given by the following equation:
fSW 1 2REFFCOUT REFF 1 2fSWCOUT
REFF = RESR + A CSRCS where COUT is the total output capacitance, RESR is the total ESR of the output capacitors, RCS is the currentsense resistance, and ACS is the current-sense gain as determined by the ILIM setting. ACS equals 2, 2.67, 4, and 8 for ILIM settings of 5V, 3.3V, 2V, and GND, respectively. For a 300kHz application, the effective zero frequency must be well below 95kHz, preferably below 50kHz. For the standard application circuit with ceramic output capacitors, the output ripple cannot be relied upon to be in phase with the inductor current due to the low ESR of the ceramic capacitors. Stability is mainly dependent on the current-sense gain. With ILIM = 2V, ACS = 4, and an effective current-sense resistance of approximately 3.5m, then the ESR zero works out to: 1/[2 x (2 x 330F + 5 x 10F) x 4 x 3.5m] = 16kHz This is well within the stability requirements.
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers
When only using ceramic output capacitors, output overshoot (VSOAR) typically determines the minimum output capacitance requirement. Their relatively low capacitance value can allow significant output overshoot when stepping from full-load to no-load conditions, unless designed with a small inductance value and high switching frequency to minimize the energy transferred from the inductor to the capacitor during load-step recovery. Unstable operation manifests itself in two related but distinctly different ways: double pulsing and feedback loop instability. Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This "fools" the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot. input. If the Quick-PWM controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than +10C temperature rise at the RMS input current for optimal circuit longevity.
MAX17007A/MAX17008
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Calculate both of these sums. Ideally, the losses at VIN(MIN) should be roughly equal to losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of NH (reducing RDS(ON) but with higher CGATE). Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider reducing the size of NH (increasing RDS(ON) to lower CGATE). If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., one or two 8-pin SOs, DPAK, or D2PAK), and is reasonably priced. Make sure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gateto-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems might occur (see the MOSFET Gate Drivers (DH, DL) section).
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. The IRMS requirements can be determined by the following equation for a single-phase application:
IRMS = ILOAD12VOUT1(VIN - VOUT1) + ILOAD22VOUT2 (VIN - VOUT2 ) VIN
MOSFET Power Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage:
V 2 PD(NHRe sistive) = OUT (ILOAD ) RDS(ON) VIN(MIN) Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power dissipation often limits how small the MOSFET can be. Again, the optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue until the input is greater than approximately 15V.
In combined mode, the input RMS current simplifies to: I IRMS = LOAD 2VOUT ( VIN - VOUT ) 2VIN where ILOAD is the combined output current of both phases. For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
Calculating the power dissipation in high-side MOSFET (NH) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: QG(SW) PD(NHSwitching) = VIN(MAX)ILOADfSW IGATE + COSS VIN(MAX)2 fSW 2 Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. Select a diode that can handle the load current during the dead times. This diode is optional and can be removed if efficiency is not critical.
Boost Capacitors
The boost capacitors (CBST) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1F ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1F. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs' gates: CBST = N x QGATE 200mV
where COSS is the NH MOSFET's output capacitance, QG(SW) is the charge needed to turn on the NH MOSFET, and IGATE is the peak gate-drive source/sink current (2.4A typ). Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied due to the squared term in the C x V IN2 x f SW switching-loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when biased from V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage: V 2 PD(NL Re sistive) = 1 - OUT (ILOAD ) RDS(ON) VIN(MAX) The worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX), but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, you can "over design" the circuit to tolerate: I ILOAD = IVALLEY(MAX) + INDUCTOR 2 ILOAD(MAX)LIR = IVALLEY(MAX) + 2 where I VALLEY(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good size heatsink to handle the overload power dissipation.
32
where N is the number of high-side MOSFETs used for one regulator, and QGATE is the gate charge specified in the MOSFET's data sheet. For example, assume (2) IRF7811W n-channel MOSFETs are used on the high side. According to the manufacturer's data sheet, a single IRF7811W has a maximum gate charge of 24nC (VGS = 5V). Using the above equation, the required boost capacitance would be: C BST = 2 x 24nC = 0.24F 200mV
Selecting the closest standard value, this example requires a 0.22F ceramic capacitor.
Applications Information
Minimum Input Voltage Requirements and Dropout Performance
The output-voltage adjustable range for continuousconduction operation is restricted by the nonadjustable minimum off-time one-shot. For best dropout performance, use the slower (200kHz) on-time settings. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the on-times. This error is greater at higher frequencies. Also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the Transient Response section (the VSAG equation) in the Quick-PWM Design Procedure section).
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers
In a single-phase configuration, the absolute point of dropout is when the inductor current ramps down during the minimum off-time (IDOWN) as much as it ramps up during the on-time (I UP ). The ratio h = I UP / IDOWN is an indicator of the ability to slew the inductor current higher in response to increased load and must always be greater than 1. As h approaches 1--the absolute minimum dropout point--the inductor current cannot increase as much during each switching cycle, and VSAG greatly increases unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between V SAG , output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: VOUT + VCHG VIN(MIN) = 1 - h x t OFF(MIN)fSW
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all the power components on the top side of the board with their ground terminals flush against one another. Follow these guidelines for good PCB layout: * Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitterfree operation. * Connect all analog grounds to a separate solid copper plane, which connects to the GND pin of the Quick-PWM controller. This includes the V CC bypass capacitor, REF bypass capacitors, REFIN1 components, and feedback compensation/dividers. Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PCBs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. Keep the high current, gate-driver traces (DL, DH, LX, and BST) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shoot-through currents. When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. Route high-speed switching nodes away from sensitive analog areas (REF, REFIN1, FB2, CSH, and CSL).
MAX17007A/MAX17008
(
)

*
where VCHG is the parasitic voltage drop in the charge path (see the On-Time One-Shot section), and tOFF(MIN) is from the Electrical Characteristics table. The absolute minimum input voltage is calculated with h = 1. If the calculated VIN(MIN) is greater than the required minimum input voltage, then reduce the operating frequency or add output capacitance to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate VSAG to be sure of adequate transient response. Dropout Design Example: VOUT = 1.5V fSW = 300kHz tOFF(MIN) = 250ns VCHG = 150mV (10A load) h = 1.5: 1.5V + 150mV VIN(MIN) = = 1.86V 1 - (0.25s x 1.5 x 300kHz) Calculating again with h = 1 gives the absolute limit of dropout: 1.5V + 150mV VIN(MIN) = = 1.78V 1 - (0.25s x 1.0 x 300kHz) Therefore, VIN must be greater than 1.78V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 2.0V.
*
*
*
Layout Procedure
1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, C IN, COUT, and anode of the low-side Schottky). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the controller IC adjacent to the low-side MOSFET. The DL gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC).
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33
Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
3) Group the gate-drive components (BST capacitors, VDD bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as shown in Figures 1 and 2. This diagram can be viewed as having four separate ground planes: I/O ground, where all the high-power components go; the power ground plane, where the PGND pin and V DD bypass capacitor go; the master's analog ground plane where sensitive analog components, the master's GND pin, and VCC bypass capacitor go; and the slave's analog ground plane where the slave's GND pin and VCC bypass capacitor go. The master's GND plane must meet the PGND plane only at a single point directly beneath the IC. Similarly, the slave's GND plane must meet the PGND plane only at a single point directly beneath the IC. The respective master and slave ground planes should connect to the high-power output ground with a short metal trace from PGND to the source of the low-side MOSFET (the middle of the star ground). This point must also be very close to the output capacitor ground terminal. 5) Connect the output power planes (VOUT and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the load as is practical. See Figure 15.
POWER STAGE LAYOUT (TOP SIDE OF PCB) KELVIN SENSE VIAS UNDER THE INDUCTOR (SEE MAX17007A EVALUATION KIT) INDUCTOR L2
OUTPUT 1 INDUCTOR L1
OUTPUT 2
COUT2
COUT2
COUT1
SMPS1
COUT1
POWER GROUND
CSL CSH
CIN2
Figure 15. PCB Layout Example
34 ______________________________________________________________________________________
CIN1
INPUT VIA TO POWER GROUND CONNECT THE EXPOSED PAD TO ANALOG GND VCC BYPASS CAPACITOR
KELVIN SENSE VIAS TO INDUCTOR PAD INDUCTOR DCR SENSING
SMPS2
CONNECT GND AND PGND THE CONTROLLER AT ONE POINT ONLY AS SHOWN X-RAY VIEW. IC MOUNTED ON BOTTOM SIDE OF PCB. + REF BYPASS CAPACITOR VIA TO ANALOG GROUND IC LAYOUT
Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers
Chip Information
TRANSISTOR COUNT: 13,103 PROCESS: BiCMOS
PACKAGE TYPE 28 TQFN
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE CODE T2844-1 DOCUMENT NO. 21-0139
MAX17007A/MAX17008
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Dual and Combinable QPWM Graphics Core Controllers for Notebook Computers MAX17007A/MAX17008
Revision History
REVISION NUMBER 0 1 2 REVISION DATE 2/08 9/08 10/08 Initial release Changed MAX17007 to MAX17007A, changed EC table, and corrected typos Released the MAX17008. Updated the EC table. DESCRIPTION PAGES CHANGED -- 1-8, 11, 12, 13, 16, 18, 24, 25 1, 3, 6
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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